1. Field of the Invention
The present invention generally relates to a mode setting circuit of a semiconductor device. More particularly, the present invention relates to a mode setting circuit of a semiconductor device which sets a tuning voltage and switches a refresh cycle using the same pads formed on a semiconductor chip.
2. Description of the Background Art
Semiconductor memory devices (DRAMs (dynamic random access memories) in particular) are classified into hundreds of and thousands of product groups according to their functions. According to a refresh cycle, for example, these devices are classified into a 8 k refresh cycle product, a 4 k refresh cycle product, and the like. A mode switching function is used for such classification. More specifically, a semiconductor device is designed to be able to carry out refresh both in a 8 k refresh cycle and in a 4 k refresh cycle, and either of the refresh cycles is selected according to the mode switching function.
FIG. 9A shows a conventional mode switching circuit which is built in a DRAM. Pads 11 and 12 for mode switching are formed on a semiconductor chip of the DRAM. Pad 11 is connected to the input of an inverter 21 and one input end of an NOR gate 32. The output of inverter 21 is connected to one input end of an NOR gate 31. Pad 12 is connected to the input of an inverter 22 and the other input end of NOR gate 32. The output of inverter 22 is connected to the other input end of NOR gate 31. A switch signal R4KE for switching to the 4 k refresh cycle is provided from the output of NOR gate 31, and a switch signal R8KE for switching to the 8 k refresh cycle is provided from the output of NOR gate 32.
FIG. 9B is a truth table for describing operation of the circuit shown in FIG. 9A. When it is desired to carry out refresh in the 8 k refresh cycle, pads 11 and 12 are set to a ground potential to attain a logical low or L level. In response to a signal at the L level, NOR gate 32 is opened, and the switch signal R8KE is output. Since outputs of inverters 21 and 22 attain a logical high or H level at this time, NOR gate 31 is closed, and the switch signal R4KE attains the L level.
When the refresh cycle is switched to the 4 k refresh cycle, pads 11 and 12 are connected to a power supply line, respectively, and attain the H level. Since both inputs of NOR gate 32 attain the H level, the gate is closed, and the switch signal R8KE attains the L level. Since the outputs of inverters 21 and 22 attain the L level, NOR gate 31 is opened, and the switch signal R4KE is set at the H level. By setting pads 11 and 12 at the H or L level as described above, any one of the two refresh cycles can be selected.
On the other hand, in the DRAM, in order to improve the reliability, an external power supply voltage is down-converted to a desired potential in the semiconductor device, or a tuning circuit is used for readjusting an internal voltage (substrate voltage, for example) changed by variation in the manufacturing process to a desired value. Improvement of the characteristics of the semiconductor device is thus pursued.
FIG. 10 is a circuit diagram showing one example of a conventional tuning circuit. In the example shown in FIG. 10, four pads 16 to 19 are used so that 16 kinds of level set signals can be provided. Referring to FIG. 10, pad 16 is connected to the input of an inverter 23, the output of inverter 23 is connected to the gate of p channel transistor 34 and the input of an inverter 24, and the output of inverter 24 is connected to the gate of an n channel transistor 33. Pad 17 is connected to the input of an inverter 25, the output of inventer 25 is connected to the gate of a p channel transistor 36 and the input of an inverter 26, and the output of inventer 26 is connected to the gate of an n channel transistor 35. Pad 18 is connected to the input of an inventer 27, the output of inverter 27 is connected to the gate of a p channel transistor 38 and the input of an inverter 28, and the output of inventer 28 is connected to the gate of an n channel transistor 37. Pad 19 is connected to the input of an inverter 29, the output of inverter 29 is connected to the gate of a p channel transistor 40 and the input of an inverter 30, and the output of inverter 30 is connected to the gate of an n channel transistor 39.
Further, a p channel transistor 42 is connected in parallel with n channel transistor 33 and p channel transistor 34, a p channel transistor 43 is connected in parallel with n channel transistor 35 and p channel transistor 36, a p channel transistor 44 is connected in parallel with n channel transistor 37 and p channel transistor 38, and a p channel transistor 45 is connected in parallel with n channel transistor 39 and p channel transistor 40. These p channel transistors 42 to 45 are connected in series, with their gates grounded. A p channel transistor 41 is connected between the drain of n channel transistor 42 and a power source. A level set signal is output from the connection point between p channel transistors 41 and 42.
FIG. 11 shows the relationships between inputs at respective pads and level set signals in the tuning circuit shown in FIG. 10. The tuning circuit shown in FIG. 10 can select 16 kinds of level set signals by setting four pads 16 to 19 to the L or H level as shown in FIG. 11. Based on these level set signals, the tuning circuit can set the internal voltage to a desired potential.
However, providing the conventional mode switching circuit and the conventional tuning circuit within one DRAM causes the number of pads to be increased, which in turn increases the chip area.